(1) Field of the Invention
The present invention relates to analyzers and in particular to an analyzer having a scan test function.
(2) Description of the Related Art
Known are methods using a scan path in order to facilitate a test in a semiconductor integrated circuit, in particular, a large scale logic circuit. Regarding a scan path composed of flip-flops (referred to simply as FFs hereinafter), the FFs function as a shift register when a scan test is performed, apart from ordinary logic used at the time of actual operation. This makes it possible to set predetermined values in the FFs inside the circuit from, for example, input terminals for test without being affected by the internal logic in the circuit, when the circuit is in a mode to operate a scan test (hereinafter referred to as scan mode). Moreover, values of the FFs inside the circuit can be outputted to output terminals for test.
However, with the conventional analyzer using a scan path that is incorporated in a semiconductor integrated circuit, it is difficult to continuously operate the circuit after data in FFs inside the circuit is read out and analyzed. To cope with this problem, known are methods of feeding back an output signal from a scan path to the input of the scan path (see, for example, Japanese Unexamined Patent Application Publication No. 2003-344502).
A conventional analyzer using a scan path, described in Japanese Unexamined Patent Application Publication No. 2003-344502, will be described hereinafter. FIG. 1 is a block diagram illustrating the configuration of the conventional analyzer.
The analyzer 900 illustrated in FIG. 1 has scan paths 901a and 901b, selectors 904a and 904b, and a dummy FF (flip-flop) 906.
The scan paths 901a and 901b are circuits for scan test, integrated into an actual operation circuit. The scan paths 901a and 901b operate as a shift register in the scan mode, and perform a shift operation in accordance with clocks 902. In the scan path 901b, the number of stages in the FFs therein is smaller than that of the FFs in the scan path 901a. 
The dummy FF 906 is an FF that is not used in actual operation. The number of stages in the FFs in the scan path 901a is equal to the sum of that of the FFs in the scan path 901b and that of the dummy FF 906.
The selector 904a selects a scan path output 903a, which is an output from the scan path 901a, or a scan path input 905a, and then connects the selected one to the input of the scan path 901a. The selector 904b selects a scan path output 903b, which is an output from the scan path 901b, or a scan path input 905b, and then connects the selected one to the input of the scan path 901b. 
In the scan mode, the selectors 904a and 904b select the scan path outputs 903a and 903b, respectively. The scan paths 901a and 901b each performs shift operation whenever one of the clocks 902 is inputted thereto, so that values of the FFs in the internal circuit (i.e., values of the FFs in the scan paths 901a and 901b) are sequentially outputted as the scan path outputs 903a and 903b, respectively. When the clocks 902 the number of which is equal to the number of stages in the FFs included in the scan path 901a are inputted to the analyzer, values of the FFs included in the scan paths 901a and 901b become the same values as those when the scan test starts (when the end of the actual operation mode). In this manner, it becomes possible to carry out actual operation continuously after the scan mode. Furthermore, providing the dummy FF 906 makes it possible that, although the analyzer has scan paths in which the numbers of stages in the FFs therein are different from each other, values of the FFs included in the scan paths are returned to the values when the scan test starts, by using the same number of clocks.